Generally speaking, a liquid crystal display device or an organic EL display device of an active matrix type includes: a substrate on which a thin film transistor (Thin Film Transistor; hereinafter “TFT”) is formed as a switching element for each pixel (hereinafter a “TFT substrate”); a counter substrate on which a counter electrode, color filters, and the like are formed; and an optical modulation layer, e.g., a liquid crystal layer, provided between the TFT substrate and the counter substrate.
On the TFT substrate, a plurality of source lines, a plurality of gate lines, and a plurality of TFTs respectively disposed at intersections therebetween, pixel electrodes for applying a voltage across the optical modulation layer such as a liquid crystal layer, storage capacitor lines and storage capacitor electrodes, and the like are formed. Moreover, at an end portion of the TFT substrate, terminal portions for allowing the source lines and gate lines to be respectively connected to input terminals of a driving circuit are provided. The driving circuit may be formed on the TFT substrate, or on a separate substrate (circuit board).
The construction of a TFT substrate is disclosed in Patent Document 1, for example. Hereinafter, with reference to the drawings, the construction of a TFT substrate disclosed in Patent Document 1 will be described.
FIG. 12(a) is a schematic plan view showing the TFT substrate in outline, and the FIG. 12(b) is an enlarged plan view showing one pixel of the TFT substrate. FIG. 13 is a cross-sectional view of a TFT and terminal portions of the semiconductor device shown in FIG. 12.
As shown in FIG. 12(a), the TFT substrate includes a plurality of gate lines 2016 and a plurality of source lines 2017. Each region 2021 surrounded by these lines 2016 and 2017 defines a “pixel”. In a region 2040 of the TFT substrate other than the region (displaying region) where the pixels are formed, a plurality of connecting portions 2041 for allowing the plurality of gate lines 2016 and source lines 2017 to be respectively connected to a driving circuit are provided. Each connecting portion 2041 constitutes a terminal portion for providing connection to external wiring. In the present specification, the region 2040 of the TFT substrate in which a plurality of terminal portions are provided is referred to as a “terminal deployment region”. As shown in FIG. 12(b) and FIG. 13, a pixel electrode 2020 is provided so as to cover each region 2021 defining a pixel. Moreover, a TFT is formed in each region 2021. The TFT includes a gate electrode G, gate insulating films 2025 and 2026 covering the gate electrode G, a semiconductor layer 2019 disposed on the gate insulating film 2026, and a source electrode S and a drain electrode D respectively connected to both end portions of the semiconductor layer 2019. The TFT is covered by a passivation film 2028. An interlayer insulating film 2029 is formed between the passivation film 2028 and the pixel electrode 2020. The source electrode S of the TFT is connected to a source line 2017, whereas the gate electrode G is connected to a gate line 2016. The drain electrode D is connected to the pixel electrode 2020 within a contact hole 2030.
Moreover, a storage capacitor line 2018 is formed in parallel to the gate line 2016. The storage capacitor line 2018 is connected to a storage capacitor. Herein, the storage capacitor is composed of a storage capacitor electrode 2018b which is made of the same conductive film as the drain electrode, a storage capacitor electrode 2018a which is made of the same conductive film as the gate line, and the gate insulating film 2026 interposed therebetween. On the connecting portion 2041 extending from each gate line 2016 or source line 2017, the gate insulating films 2025 and 2026 and the passivation film 2028 are not formed, but a connection line 2044 is formed so as to be in contact with an upper face of the connecting portion 2041. As a result, electrical connection between the connecting portion 2041 and the connection line 2044 is ensured.
As shown in FIG. 13, in the liquid crystal display device, the TFT substrate 2013 is disposed so as to oppose a substrate 2014 on which a counter electrode and color filters are formed, with a liquid crystal layer 2015 interposed therebetween.
When fabricating such a TFT substrate, the regions 2021 to become pixels (also referred to as “pixel portions”) and the terminal portions are preferably formed through a common process, so as to reduce increase in the number of masks and the number of steps.
In order to fabricate the aforementioned TFT substrate, it is necessary to etch away the portions of the gate insulating films 2025 and 2026 and the passivation film 2028 that are located in the terminal deployment region 2040, and the portions of the gate insulating film 2025 and the passivation film 2028 that are located in the regions where the storage capacitors are to be formed. Patent Document 1 discloses forming an interlayer insulating film 2029 by using an organic insulating film, and by using this as a mask, etching the insulating films 2025 and 2026 and the passivation film 2028.
On the other hand, it has been proposed in the recent years to form an active layer of a TFT by using an oxide semiconductor film such as zinc oxide, instead of a silicon semiconductor film. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has higher mobility than does amorphous silicon. Therefore, an oxide semiconductor TFT is able to operate more rapidly than an amorphous silicon TFT. Moreover, an oxide semiconductor film is formed through simpler processes than those of a polycrystalline silicon film, and therefore is also applicable to devices which require a large area.
However, during the production process of an oxide semiconductor TFT having a bottom-gate structure, carrier electrons may occur due to oxygen defects in a heat treatment step or the like, for example, thus resulting in lower resistance. There is also a problem in that the underlying oxide semiconductor film is susceptible to damage in the steps of etching source/drain electrodes and the step of forming an interlayer insulating film.
On the other hand, a structure (channel-protection type) has been proposed in which a channel protection film is provided so as to cover the region of a semiconductor layer where a channel is to be formed (channel-forming region). In a TFT production process, when forming source/drain electrodes after a channel protection film is formed on the semiconductor layer, the channel protection film functions as an etchstop in performing an etching for forming the source/drain electrodes. As a result, the damage which the channel-forming region receives through etching can be reduced.
Patent Document 2 describes the construction of a pixel portion of a TFT substrate having channel-protection type TFTs. However, the TFTs of Patent Document 2 are formed by using a silicon film.
FIG. 14 is a cross-sectional view showing a portion of the TFT substrate described in Patent Document 2. In each pixel of the TFT substrate, a thin film transistor 1141 and a storage capacitor 1142 are provided. In the thin film transistor 1141, a gate line 1102, a gate insulating film 1104, a semiconductor layer 1113 having a channel-forming region, a channel protection film 1108, a source region 1118, a drain region 1117, and a drain electrode 1121 and a source line 1122 are formed. The thin film transistor 1141 is covered by a passivation film 1127, and a pixel electrode 1131 is provided on the passivation film 1127. Within a contact hole which is formed in the passivation film 1127, the pixel electrode 1131 is connected to the drain electrode 1121. The storage capacitor 1142 is composed of the gate insulating film 1104 and the passivation film 1127 interposed between the electrodes as the dielectric, with the electrodes being a capacitor line 1151 which is formed of the same conductive film as the gate line 1102 and the pixel electrode 1131.
In the present specification, an insulating film which is formed between a channel-forming region and a source/drain electrode of a semiconductor layer is referred to as a “channel protection film” or an “etch stopper”, whereas any insulating film covering a TFT, or an insulating film which is formed on source/drain electrodes in the case of a bottom-gate structure, is simply referred to a “passivation film” for distinction between them.
Although not shown, in a terminal portion of this TFT substrate, the gate line 1102 can be electrically connected to external wiring which is provided on the passivation film 1127, within a contact hole which is formed in the passivation film 1127 and the gate insulating film 1104 over the gate line 1102.
In the aforementioned method for producing a semiconductor device, an etching for forming the channel protection film 1108, an etching for forming the source/drain electrodes 1121 and 1122, and an etching for forming a contact hole in the passivation film 1127 are performed (FIG. 7 to FIG. 9 of Patent Document 2). It is considered that the contact hole in the terminal portion is formed by allowing the passivation film 1127 and the gate insulating film 1104 to be etched at one time when etching the passivation film 1127.
In Patent Document 3, use of halftone masks is proposed in the method of producing the TFT substrate having channel-protection type TFTs, this being in order to reduce the number of masks to be used. However, the method of Patent Document 3 involves a complicated production process, and may lower the mass producibility. Moreover, because only one layer of insulating film is formed between the gate electrode and the source/drain electrodes, there is a possibility that short-circuiting may occur between these electrodes.